1. Field of the Invention
This invention relates to semiconductor chip packaging technology, and more particularly to an ultra-thin semiconductor package and a method for manufacturing the same. This invention also relates to an electronic apparatus including an ultra-thin semiconductor package device.
2. Description of Related Art
In general, integrated circuit (IC) semiconductor chips such as memory chips are assembled in a package form and mounted on a circuit board of one of various electronic apparatuses. An interfacing structure is required to provide the electrical and physical interconnection between the IC chips and the circuit board. Lead frames are presently the most widely used interfacing structure in the semiconductor industry.
FIG. 1 is a cross-sectional view of a conventional IC device in which semiconductor chips are mounted on both sides of a lead frame in order to improve a mounting density of the package. This package structure is disclosed, for instance, in Japanese Unexamined Patent Publication No. 62-147360.
Referring to FIG. 1, a conventional semiconductor package 10 includes a die pad 13 and a lead frame 15 having a plurality of leads 14. A semiconductor IC chip 11 is bonded to the die pad 13 by an adhesive 12. The semiconductor IC chip 11 is electrically interconnected to the leads 14 via bonding wires 16. The semiconductor IC chip 11 and bonding wires 16 are protected by a package body 17 made of an epoxy molding compound. Outer portions of the leads 14, which protrude from the package body 17, are bent in a form suitable for mounting the package onto a circuit board (not shown).
In the conventional semiconductor package 10, there is an increasing demand for thinner packages as smaller and lighter electronic apparatuses that employ package devices are developed. In particular, when two or more semiconductor chips 11 are stacked together in a single package body to increase memory capacity, a thinner package becomes even more important.
In order to make the semiconductor package thinner, reduction of the thickness of the semiconductor chip itself and reduction of the thickness of the lead frame have been considered. For instance, by applying a so-called wafer back lapping to a wafer, semiconductor chips can be made as thin as between 100 to 150 μm. Using chips having this range of thickness, the overall thickness of the package device can be reduced to less than 1 mm.
Unfortunately, however, since the wafer is made of low-hardness material such as silicon, reducing the thickness of the semiconductor chip makes handling of the wafer more difficult and increases the possibility of chip cracks or wafer warpage. As a result, there are inevitable limitations on decreasing the thickness of the semiconductor chip; especially considering that the demand for improving yield of semiconductor products has resulted in an increases in the diameter of wafers to about 12 inches.
Reducing the thickness of the lead frame also has disadvantages. For example, if the thickness of a lead frame is too small, the lead frame is very fragile, leading to a decrease in the productivity of the assembly process. Based on the need for handling lead frames and for forming outer leads, 100 μm is a known limit on the thinness of the lead frame.
Conventional instruments and plastic packaging machinery are widely used for packaging semiconductor devices. Unfortunately, however, when new assembly technologies such as CSP (Chip Scale or Size Package) technology are used to make the package device thinner, costs for replacing existing instruments and machinery are incurred.